Patent portfolio

Four provisional applications. One validation thesis.

Sunaiva's products are commercial embodiments of a filed provisional patent family. References below use USPTO Provisional application numbers — these are filed applications, not granted patents.


USPTO 64/006,491

Mandatory Real-Time AI Output Validation System with Multi-Gate Cryptographic Enforcement

Filed 2026-03-16 Claims 28 Deadline 2027-03-16

Defines a validation system in which AI output is checked by a plurality of independent scoring gates whose passing results are combined under conjunctive AND-logic, where the validation is invokable by the generating model during generation via tool-calling, and where a composite cryptographic proof binds the individual gate signatures, an output hash and a timestamp. This is the foundation patent — the Triple-Gate Validation MCP is its Claim 1 commercial embodiment, and the Gate enforces agent actions under Claim 22.

USPTO 64/030,391

Self-Validating Multi-Agent Distribution System with Coprime Completeness and Post-Quantum Signing

Filed 2026-04-06 Deadline 2027-04-06

Describes a distribution system in which multiple agents self-validate work products, using a coprime completeness scheme to guarantee coverage across a partitioned task space, with artifacts signed by post-quantum signature algorithms so that validity survives a future cryptographically-relevant quantum adversary. The architecture lets a fleet of agents prove collectively that no required region of work was skipped or duplicated.

USPTO 64/030,411

Quantum-Resistant Trustless Commerce System with Triple-Algorithm Financial Attestation

Filed 2026-04-06 Deadline 2027-04-06

Covers a trustless commerce mechanism in which a financial transaction is attested by three independent cryptographic algorithms in concert, such that settlement is only acknowledged when all three attestations agree, and where the algorithm selection is quantum-resistant. The triple-algorithm requirement removes single-algorithm failure as a path to forged settlement.

CIP of 64/006,491

Hardware-Attested Multi-Gate AI Output Validation System with Cross-Vendor TEE Interoperability

Filed 2026-05-17

A continuation-in-part of the foundation patent that anchors gate evaluation inside hardware-attested execution: gate logic runs in a trusted execution environment, the attestation key is HKDF-derived, and the scheme is interoperable across Intel TDX, AMD SEV-SNP, NVIDIA Confidential Compute, ARM TrustZone and Apple Secure Enclave. This is the basis for the hardware attestation option on enterprise tiers.

Status Filed 2026-05-17. Confidential by statute — provisional applications are not published in USPTO databases.
Patent details are based on filed provisional applications. Track status at patentcenter.uspto.gov.